This invention relates generally to logic circuits of the type fabricated on a monolithic silicone semiconductor chip of an integrated circuit and more particularly, it relates to master-slave D-type flip-flop circuits having an improved voltage offset means for creating a separation of thresholds between the master section and the slave section in the flip-flops.
As is well known, one form of flip-flops useful in digital logic applications is a direct coupled master-slave D-type flip-flop which is sometimes referred to as en edge-triggered D-type flip-flop. Such a flip-flop has a single data input (D input), a pair of complementary data outputs (Q and Q), and a clock input (CLK). Data in the form of a logic level present at the data input (D input) is updated or transferred to the master section when the clock input (CLK) is at the low or "0" logic level. The data is then transferred to the slave section when the clock input CLK makes a transition from the low logic level to a high or "1" logic level. When the clock input CLK changes from the high state back to the low state, the logic state present in the slave section prior to the clock transition is retained or latched at the complementary data outputs (Q and Q). This latched condition remains regardless of subsequent changes in the data input until such time the clock input CLK means another low-to-high transition.
In order to prevent false information or data from being transferred directly from the master section to the slave section during the clock transition, particularly if the D input is changing at this transition time, there has been provided in the flip-flop of the prior art an offset means for creating a separation of thresholds between the reference voltages in the master and slave sections. Such a typical prior art master-slave D-type flip-flop is illustrated in FIG. 1 of the drawings and has been labeled "Prior Art." This flip-flop 10 is commerically available from Motorola, Inc., of Schaumburg, Ill. under their Part No. designation of MC 1670. The offset voltage between the thresholds of the pair of differentially connected transistors 1Q2/1Q3 in the master section and the pair of differentially connected transistors 2Q2/2Q3 in the slave section of the flip-flop 10 is achieved by an offset resistor R8 and its associated circuit components. While this prior art flip-flop performs adequately the function of preventing the false transferring of data, it suffers from the disadvantage of requiring the use of a resistor R8 which occupies a relatively large amount of chip area. Further, this flip-flop 10 has the disadvantage in that it needs a relatively large number of circuit components in order to implement the offset in the thresholds, thereby increasing the overall power consumption.
It would therefore be advantageous to increase the economy of manufacturing these master-slave D-type flip-flop circuits and to decrease the amount of chip area required. It would also be expedient to provide a flip-flop having a separation of thresholds between the master and slave sections which is formed with a smaller number of circuit components than those that are traditionally available. It would also be expedient to provide such a flip-flop which utilizes a smaller amount of chip area and has a reduced amount of power consumption.